The switched mode power supply (SMPS) is a well-known type of power converter having a diverse range of applications by virtue of its small size and weight and high efficiency, for example in personal computers and portable electronic devices such as cell phones. A SMPS achieves these advantages by switching one or more switching elements such as power MOSFETs at a high frequency (usually tens to hundreds of kHz), with the frequency or duty cycle of the switching being adjusted by a feedback loop (also widely referred to as a “compensation loop” or “feedback circuit”) to convert an input voltage to a desired output voltage. An SMPS may take the form of a rectifier (AC/DC converter), a DC/DC converter, a frequency changer (AC/AC) or an inverter (DC/AC).
Increasing dynamic requirements, such as monotonic start-up, recovery after short-circuit, load transient performance, have led to the relocation of the control circuits of many modern isolated switched mode power supplies from the primary side to the secondary side of the SMPS. When the control circuit is on the secondary side of the isolation barrier, some means of powering it from the primary side needs to be provided, and the input voltage needs to be monitored accurately, since it is used in the control of the main converter of the SMPS.
The control circuit of an isolated SMPS is often powered via an auxiliary (or ‘housekeeping’) converter. There are numerous of ways of designing such an auxiliary converter.
For example, FIG. 1 provides a schematic illustration of an SMPS 11 comprising a main converter 12 for converting an input voltage Vin to an output voltage Vout, a drive circuit 15 for driving the converter 12, a controller 16 for controlling the drive circuit 15 (for example, by controlling the switching duty cycle or the switching frequency of one or more switching elements, such as field-effect transistors (FETs), in the drive circuit 15) and thus the operation of the main converter 12, and an auxiliary converter 17 for down-converting the input voltage Vin to a voltage suitable for powering the controller 16. Such an auxiliary converter 17 may supply power to the primary side circuits of the SMPS 11 and provide an isolated power supply to secondary side circuits of the SMPS 11. The auxiliary converter 17 may also send information about the input voltage Vin to secondary side circuits, such as controller 16, which information may be used for voltage feed-forward in an SMPS controlled from the secondary side, or for setting a reference voltage in a switched mode power supply being controlled in the regulated ratio (RR) mode or the hybrid regulated ratio (HRR) mode, as described in WO 2012/116750 A1 and WO 2013/113354 A1, for example.
The main converter 12 is an isolated DC-DC converter, typically down-converting the input voltage Vin to a suitable output voltage Vout for powering the load of the SMPS 11. The main converter 12 may typically operate with an input or output voltage range of 10-100 V.
The auxiliary converter 17 may be provided in the form of a fly-buck converter. FIG. 2 illustrates an isolated fly-buck converter, which can be used as the auxiliary converter 17 in the SMPS of FIG. 1.
The fly-buck converter is configured to convert the input voltage Vin to a secondary side output voltage VS, and comprises a primary winding X1, a non-isolated buck CP, and a pair of switches Q1, Q2 on a primary side of the converter. A secondary winding X2, a first capacitive element CS, and a first rectifying element D1 are provided on the secondary side of the converter. While isolated fly-buck converters typically have a transformer ratio between the first and secondary windings of 1:1, field-effect transistors, which may be used in controller 16, usually require lower voltages. Therefore, a suitable converter ratio for the isolated fly-back converter may be 1:0.75.
The non-isolated buck CP (which may be provided in the form of a capacitor, for example) is connected in series with the primary winding X1 and the pair of switching elements Q1, Q2 (e.g. FETs such as MOSFETs) arranged in the primary side circuit. The switching elements Q1, Q2 are configured to switch such that, during a forward phase of operation of the isolated fly-buck converter, the primary winding X1 and the non-isolated buck CP are connected to the input voltage Vin and, during a fly-buck phase of operation of the isolated fly-buck converter, the primary winding X1 and the non-isolated buck CP are disconnected from the input voltage and are connected to one another in a closed circuit. The switching of the switching elements Q1, Q2 may be controlled by a switching controller (not illustrated).
The secondary winding X2 is electromagnetically coupled to the primary winding X1. The first capacitive element CS, which may be provided in the form of a capacitor, is connected over the secondary winding X2. The first rectifying element D1, which may be provided in the form of a diode, is connected to the secondary winding X2 and the first capacitive element CS so as to prevent current from flowing through the secondary winding X2 to charge/discharge the first capacitive element CS during the forward phase of operation of the fly-buck converter. The output voltage VS of the fly-buck converter corresponds to the voltage over the first capacitive element CS.
A modified form of the above-described fly-buck converter, which allows a reliable measurement of the input voltage to be made on the secondary side, is described in WO 2015/137852 A1. The circuit diagram of this modified fly-buck converter is illustrated in FIG. 3.
As shown in FIG. 3, the modified fly-buck converter is additionally provided with an input voltage sensing circuit for generating a voltage Vsense that is indicative of the input voltage Vin. The input voltage sensing circuit comprises a second capacitive element CF (e.g. implemented as a capacitor) and a second rectifying element D2 (e.g. implemented as a diode) that are connected in series. The input voltage sensing circuit is connected over the secondary wiring X2 such that the second rectifying element D2 prevents current from flowing through the input voltage sensing circuit during the fly-buck phase. The sum of the voltage VF over the second capacitive element CF and the output voltage VS is the sensed measure Vsense on the secondary side, which is indicative of the input voltage Vin on the primary side. The input voltage sensing circuit may, as in the example of FIG. 3, comprise a resistive element R3 connected in series with the second capacitive element CF and the second rectifying element D2, the resistive element R3 serving to reduce current spikes during charging of the second capacitive element CF, thereby producing a less noisy voltage over second capacitive element CF.
To further explain the operation of the modified fly-buck converter shown in FIG. 3, the relation between the sensed voltage Vsense and the input voltage Vin will be derived in the case where the primary winding X1 has one winding and the secondary winding X2 is taken to have n windings. Steady-state switching with a duty cycle D, a small ripple current in the windings, and a small voltage ripple in the capacitances are also assumed.
During the forward phase, wherein the switching element Q1 is conducting and the switching element Q2 is off, the fly-buck converter of FIG. 3 can be simplified to the circuit diagram shown in FIG. 4a, since the rectifying element D1 becomes non-conducting. For simplicity, the resistive element R3 is removed during this analysis.
The voltage over the inductor can be stated directly on the primary side asVL=Vin−VP,  Equation 1or, using the reflected voltage over the second capacitive element VF on the primary side, as
                                          V            L                    =                                                    V                F                            +                              V                D                                      n                          ,                            Equation        ⁢                                  ⁢        2            where VD is the voltage drop over the diode D2 in the forward direction.
During the fly-buck phase, the fly-buck converter of FIG. 3 can be simplified to the circuit diagram shown in FIG. 4b. 
The voltage over the primary winding X1 can be stated directly on the primary side asVL=−VP,  Equation 3or, using the reflected output voltage VS on the primary side, as
                                          V            L                    =                      -                                                            V                  S                                +                                  V                  D                                            n                                      ,                            Equation        ⁢                                  ⁢        4            where VD is the voltage drop over the diode D1 in the forward direction.
For the non-isolated buck voltage VP, the volt-second balance using Equations 1 and 3 becomesD(Vin−VP)+D′(−VP)=0,  Equation 5where the forward phase duration is equal to the duty cycle D, and the fly-buck duration is (1−D)=D′. Solving Equation 5 for VP yieldsVP=DVin.  Equation 6
For the isolated fly-buck, the volt-second balance using Equations 1 and 4 becomes
                                          D            ⁡                          (                                                V                                      i                    ⁢                                                                                  ⁢                    n                                                  -                                  V                  P                                            )                                +                                    D              ′                        ⁡                          (                              -                                                                            V                      S                                        +                                          V                      D                                                        n                                            )                                      =        0.                            Equation        ⁢                                  ⁢        7            
Collecting terms on each side yields
            DV              i        ⁢                                  ⁢        n              =                  DV        P            +                        D          ′                ⁢                                            V              S                        +                          V              D                                n                      ,and using Equation 6 yields
      V    P    =            DV      P        +                  D        ′            ⁢                                                  V              S                        +                          V              D                                n                .            
Collecting VP on the left-hand side and using (1−D)=D′ yields
            D      ′        ⁢          V      P        =            D      ′        ⁢                                        V            S                    +                      V            D                          n            .      
Dividing this by D′ on both sides and solving for VS yieldsVS=nVP−VD.  Equation 8
For the isolated forward-buck, the volt-second balance using Equations 2 and 3 becomes
                                          D            ⁢                                                  ⁢                                                            V                  F                                +                                  V                  D                                            n                                +                                    D              ′                        ⁡                          (                              -                                  V                  P                                            )                                      =        0.                            Equation        ⁢                                  ⁢        9            
Solving Equation 1 for D′(−VP) and replacing in Equation 9 yields
            D      ⁢                          ⁢                                    V            F                    +                      V            D                          n              +          D      ⁡              (                              V                          i              ⁢                                                          ⁢              n                                -                      V            P                          )              =  0.
Solving for VF yieldsVF=n(Vin−VP)−VD.  Equation 10
The sensed voltage Vsense indicative of the input voltage Vin is the sum of the voltages VS and VF, and using Equations 8 and 10 yieldsVsense=VS+VF=nVP−VD+n(Vin−VP)−VD,and collecting terms yieldsVsense=nVin−2VD.  Equation 11
Hence, the sensed voltage Vsense is linear in the input voltage Vin and offset by two diode forward voltages VD. Since the input voltage Vin times the ratio n is much greater than 2VD, Equation 11 can be simplified toVsense≈nVin.  Equation 12
The diode voltage drops can be reduced using Schottky diodes or can even be eliminated by using synchronous rectification.
The sensed voltage Vsense indicative of the input voltage Vin and sensed on the isolated secondary side can be used in the control of the main converter 12 of the switched mode power supply 11.
The controller 16 of the switched mode power supply 11 may thus be configured to receive the sensed voltage Vsense or a voltage indicative thereof, from the isolated secondary side of the auxiliary converter 11, i.e. the above-described fly-buck converter, and to control the drive circuit 15 and thus the voltage conversion performed by the main converter 12 on the basis of the sensed voltage Vsense.
The sensed voltage Vsense as measured on the secondary side, may then be used for voltage feedforward control in a secondary-side controlled switched mode power supply. Alternatively or additionally, the sensed voltage Vsense may be used for setting the reference voltage in a regulated ratio or hybrid regulated ratio controlled switched mode power supply.
FIG. 5 illustrates another isolated fly-buck converter disclosed in WO 2015/137852, which is an extension of the converter of FIG. 3 and may be used for hybrid regulated ratio (HRR) control in the switched mode power supply of FIG. 1.
The isolated fly-buck converter of FIG. 5 comprises, on the secondary side, a voltage divider including two serially-connected resistive elements, R1 and R2, that are connected in parallel over the first and second capacitive elements CS and CF to divide the sensed voltage Vsense. A fourth capacitive element, C1 (which may be provided in the form of a capacitor), and a voltage reference (voltage-limiting element) Vref are connected in parallel over one of the resistive elements of the voltage divider (namely, R1), wherein a voltage VR over the voltage reference Vref changes with a time constant that is dependent upon the fourth capacitive element C1. The voltage VR is usable as a hybrid regulated ratio reference in hybrid regulated ratio (HRR) control of the main converter 12.
In the fly-buck converter of FIG. 5, the voltage Vsense≈nVin is divided using the potential divider comprising R1 and R2, and a time constant is set by the capacitor C1. The reference voltage is saturated using a high precision voltage reference Vref, yielding the voltage for hybrid regulated ratio as
                              V          R                =                  min          (                                                                                          R                    1                                                                              R                      1                                        +                                          R                      2                                                                      ·                                  1                                      1                    +                                                                  sC                        1                                            ⁢                                                                                                    R                            1                                                    ⁢                                                      R                            2                                                                                                                                R                            1                                                    +                                                      R                            2                                                                                                                                                          ⁢                              nV                                  i                  ⁢                                                                          ⁢                  n                                                      ,                          V              ref                                )                                    Equation        ⁢                                  ⁢        13            where s is a complex frequency, the regulated ratio input voltage part has the gain GRR of
                              G          RR                =                  n          ⁢                                          ⁢                                    R              1                                                      R                1                            +                              R                                  2                  ⁢                                                                                                                                                Equation        ⁢                                  ⁢        14            and the time constant τRR becomes
                              τ          RR                =                              C            1                    ⁢                                                                      R                  1                                ⁢                                  R                  2                                                                              R                  1                                +                                  R                  2                                                      .                                              Equation        ⁢                                  ⁢        15            